The present invention generally relates to non-volatile memory components used in computer and other processing apparatus for permanent storage of data. More particularly, this invention relates to resistive memory devices and a process of secure erasing of all data stored thereon through specific commands.
Mass storage devices such as advanced technology attachment (ATA) or small computer system interface (SCSI) drives are rapidly adopting non-volatile solid-state memory technology such as flash memory or other emerging solid-state memory technology, including phase change memory (PCM), magnetoresistive random access memory (MRAM), ferromagnetic random access memory (FRAM), organic memories, or nanotechnology-based storage media such as carbon nano-fiber/nano-tube based substrates. Currently the most common technology uses NAND flash memory as inexpensive storage memory.
Despite all its advantages with respect to cell density and cost per bit, flash memory is approaching its limit with respect to scalability. More precisely, during each program or erase cycle (P/E cycle) the dielectric layer separating the floating gate from the substrate deteriorates as a consequence program or erase mechanism used such as Fowler Nordheim tunneling or direct tunneling or hot carrier injection of either holes or electrons to the point where the cells become unreliable with respect to data retention or else can no longer be programmed or erased. Previous generations of flash memory based on single level cell (SLC) technology were be able to withstand approximately 100,000 program and erase (P/E) cycles. However, with the migration to multi-level cell technology (MLC) and smaller process geometries, this write-endurance number has declined dramatically to roughly 3-5,000 cycles, depending among other things on the amount of parity information used for error correction.
The next step in the evolution of NAND flash memory, encompassing the introduction of three bits per cell (TLC NAND flash) and further shrinking of the process geometry to the 1×nm process node has exacerbated the existing problems in that the write endurance further decreased below the 1,000 P/E cycle threshold. More importantly, additional problems started to surface in the form of capacitive coupling of word lines also referred to as word line shorting, which can render entire pages inaccessible. Aside from the other, already mentioned drawbacks, the latest generations of NAND flash also suffer from greatly reduced data retention. Depending on the specific class of flash (MLC, eMLC or TLC), data retention can be as short as 3 months.
Lower reliability may be compensated for by increasing the overall capacity of a storage device, and thereby decreasing the number and frequency of write accesses at any given cell—as long as failure is predictable and the necessary countermeasures can be taken. Nothing, however, protects the user from the “sudden death” of NAND storage devices, meaning that massive catastrophic failures may occur without any pre-warning.
Given the increasing problems of NAND flash with respect to reliability, which require ever increasing complexity of countermeasures, it is clear that alternative non-volatile memory technologies need to be developed. Aside from the aforementioned technologies, the probably most viable candidate for the next generation non-volatile or permanent memory is resistive random access memory (ReRAM).
Secure or Bulk Erase
Permanent memory is a relatively new term used in the industry to describe memory with data retention lower than a non-volatile memory. In the context of this invention permanent memory refers to data retention in the order of 1000 hours. While non-volatility or permanence of data is required for data storage, it also raises security issues in that data may fall into the wrong hands. Accordingly, one of the requirements for non-volatile and permanent memory-based storage alike, at least in enterprise applications and wherever security is an issue is the requirement for secure erase.
Secure erase is important in several different scenarios. Particularly in military applications or else in situation where user data bases may be compromised, it is mandatory that any storage media can be completely wiped of user data. Another application for Secure Erase relates to RAID configurations, where a specific drive may be assigned a specific logical unit number in an array. If the array is dismantled without clearing the configuration data on the drive, the drive may not be accessible for normal operation by a host bus adapter unless all data are cleared.
Depending on the standard applied, the storage device needs to be able to execute a command for secure erase resulting in anything from a complete invalidation of data stored in the non-volatile semiconductor memory to a complete, non-recoverable erasure of all bits stored within the array. In the case of NAND flash memory, its base architecture is as groups of daisy chained floating gate transistors lends itself to this type of fast bulk erase. Specifically, one of the limitations of NAND (and also NOR) flash memory is that the smallest erasable unit is a block, which, however, has significant drawbacks for the operation of the memory device, particularly with respect to space reclamation. In this case, erasing is done on a per-block basis by applying a high positive voltage to the substrate to generate a strong electrical field, which non-specifically draws electrons out from the floating gate of all cells into the substrate, thereby erasing all cells within a block. This non specific brute force quantum tunneling approach greatly speeds up the process, albeit at a highly inflated power envelope of approximately 100 pJ of energy per bit and still requiring up to 2,500,000 nanoseconds to complete the erase of one block while physically damaging the floating gate transistor's oxide layer.
ReRAM arrays, in contrast, are typically organized similar to DRAM arrays, meaning that individual cells are accessed for read, erase or rather overwrite, by applying a programming voltage on a per cell basis, thereby providing much better granularity for management of data. In the case of DRAM-based storage devices, there is no need for any Secure Erase since the memory itself is volatile, meaning that there is hardly any data retention.
ReRAM combines the granularity of DRAM data access with data retention in the order of 1,000 hours or greater. The access granularity, on the other hand, does not typically allow for a global or bulk erase of all cells within the array, thereby creating a risk for leaking of sensitive data in a variety of scenarios. For the purpose of security in mass deployment of ReRAM as non-volatile or permanent storage media, a mechanism and method for fast bulk erase with a low energy budget would, therefore, be highly desirable.